On/Off Ratio Limits: Practical Lower Limit for Logic Functionality

[ZeroFunGame]

TL;DR Summary

When does an on/off ratio become impractical? I've read that typical CMOS devices have an on/off ratio of 10^6-10^10. Is there a lower limit that prevents logic devices from functioning appropriately? As in, what is a practical lower limit for the on/off ratio but still enable logic functionality?

When does an on/off ratio become impractical? I've read that typical CMOS devices have an on/off ratio of 10^6-10^10. Is there a lower limit that prevents logic devices from functioning appropriately? As in, what is a practical lower limit for the on/off ratio but still enable logic functionality?

 

[HallsofIvy]

That depends upon the "uniformity" of the device. If the device were perfect you wouldn't need any space between "on" and "off". But in a real device there are always slight jumps in the voltage (or current or what ever the device is monitoring). In order to avoid functioning properly the interval must be larger than any such jump.

 

[ZeroFunGame]

That depends upon the "uniformity" of the device. If the device were perfect you wouldn't need any space between "on" and "off". But in a real device there are always slight jumps in the voltage (or current or what ever the device is monitoring). In order to avoid functioning properly the interval must be larger than any such jump.

Is there a formula that quantifies this? Seems to me like it would be a function a temperature.

 

[berkeman]

When does an on/off ratio become impractical?

The ratio can be infinite, assuming you have enough patience.

Are you asking what the minimum pulse width is that can be generated by CMOS logic?

 

[Baluncore]

Fast CMOS logic requires that the gate voltage thresholds separating on and off be narrow and so quick to transit.
There is also a competing need to minimise current flowing through the off transistor of the pair.
The current I_on/I_off ratio is a measure of the design quality.

 

[Baluncore]

When does an on/off ratio become impractical?

When the ratio is high, the static current consumption is low, the gate voltage transition is wide, so the gate is slow.
When the ratio is low, the current consumption is high, the gate voltage transition is narrow, but the gate is fast.

The tradeoff is between static current consumption and speed. The practical limit to current ratio depends on the application, does it require speed or low power.

 

[Borek]

On/off means square wave, combined with high frequencies makes me think about ringing and Gibbs phenomenon.

 

[Baluncore]

It would it have helped if the word current had appeared in post #1.
The I_on/I_off ratio is a figure of merit for switches.

 

[ZeroFunGame]

Yes, I meant to say Ion/Ioff ratio.

For example, can logic circuits be built with an Ion/Ioff ratio of 1000? 100? 10? 2?

Where is the limit and why? Is there a rule of thumb? Trying to understand if there's a quantitative rational for a minimum Ion/Ioff ratio

 

[berkeman]

Where is the limit and why? Is there a rule of thumb? Trying to understand if there's a quantitative rationale for a minimum Ion/Ioff ratio

(fixed one typo in your post)

One limitation is that when you are designing ICs with CMOS gates and logic, you are trying to use the smallest geometry (smallest feature size) available, so your die are smaller which makes them cheaper to make, in general. If you try to use too cutting-edge of a geometry, there can be other costs that offset the increased number of die, but as long as you stay with the smallest standard process/geometry for your type of IC, that usually helps to minimize the cost per die.

But as you go to smaller and smaller geometries, the leakage current of the transistors increases. In fact you reach a point where the power consumption due to leakage current is comparable to the C*f current (the switching currents to the gate capacitances). That's where your "Ioff" will start to be a larger fraction of your "Ion" current.

https://en.wikipedia.org/wiki/Moore's_law

The physical limits to transistor scaling have been reached due to source-to-drain leakage, limited gate metals and limited options for channel material. Other approaches are being investigated, which do not rely on physical scaling. These include the spin state of electron spintronics, tunnel junctions, and advanced confinement of channel materials via nano-wire geometry.[139] Spin-based logic and memory options are being developed actively labs.[140][141]

 

[ZeroFunGame]

Fabrication difficulties aside, I was think more from a circuit design perspective. Can you create functional ICs using low Ion/Ioff ratios? I've read that a ratio of 100 is insufficient for CMOS logic, but was unable to understand why, and I assume this is from a noise or circuit design limitation perspective that I'm not able to abstract out to and quantify.

 

[Baluncore]

I've read that a ratio of 100 is insufficient for CMOS logic, but was unable to understand why,..

Because the idle or quiescent current when not being clocked would be higher than necessary.

With CMOS, the ON current only flows while the gate is in transition. But the leakage and OFF currents flow continuously through every transistor on the chip, always.

 

[ZeroFunGame]

Because the idle or quiescent current when not being clocked would be higher than necessary.

With CMOS, the ON current only flows while the gate is in transition. But the leakage and OFF currents flow continuously through every transistor on the chip, always.

But this just means you have higher power consumption/electrical loss. It does not necessarily limit the on/off ratio from appropriate logic functionality.

Also, you can have low loss and low drive current. Losses aren't necessarily an issue if both off state and on state have low current.

 

[Baluncore]

But this just means you have higher power consumption/electrical loss. It does not necessarily limit the on/off ratio from appropriate logic functionality.

Also, you can have low loss and low drive current. Losses aren't necessarily an issue if both off state and on state have low current.

Low ratio does not prevent operation of a single gate, but it costs more to run.

Off current heats a chip with 10 million transistors and causes thermal offsets that make the chip unreliable, hot and uncompetitive in the marketplace.

 

[ZeroFunGame]

Why would low ratio cost more to run? Typical low power Ion/Ioff is 1000 mA/mm and 1E-4 mA/mm

As mentioned before, you can have low loss and low drive current. Losses aren't necessarily an issue if both off state and on state have low current.

That is, your Ion is 1E-3 mA/mm and Ioff is 1E-4mA/mm

This is much lower power if you want to compare thermals.

The question then becomes, why is this on/off ratio insufficient? What are the limitations? Is there a cutoff point when the ratio becomes reasonable for logic applications?

 

[berkeman]

Typical low power Ion/Ioff is 1000 mA/mm and 1E-4 mA/mm

What does this mean? I don't understand your units...

That is, your Ion is 1E-3 mA/mm and Ioff is 1E-4mA/mm

This is much lower power if you want to compare thermals.

The question then becomes, why is this on/off ratio insufficient?

Why waste all that current when off? Why have an off current of 100uA when it could be in the nanoAmp range?

 

[ZeroFunGame]

What does this mean? I don't understand your units...Why waste all that current when off? Why have an off current of 100uA when it could be in the nanoAmp range?

Please see Table 7.1 here:
https://inst.eecs.berkeley.edu/~ee130/sp06/chp7full.pdf

 

[berkeman]

Please see Table 7.1 here:
https://inst.eecs.berkeley.edu/~ee130/sp06/chp7full.pdf

That's a 35 page document. What page should I be looking at?

 

[ZeroFunGame]

I said please see Table 7.1. I chose the units and values based on what is quoted from the ITRS. It's just an example to get at the heart of my question.

Going from what you said, yes, why not have an Ion of 10 nanoamps and Ioff of 1 nanoamp. The fundamental inquiry is the same.

Is this on/off ratio insufficient? Why and what are the limitations? Is there a cutoff point when the ratio becomes reasonable for logic applications?

 

[berkeman]

I said please see Table 7.1.

Oops, apologies, I missed that. So that table is on Page 2 of the document:

So you slightly mis-quoted it. The units of Ion/W are mA/mm. So it's a measure of current versus channel width, it would seem.

Ion of 10 nanoamps

Most of the current in CMOS logic is switching current, determined by the C*f values.

[tex]I(t) = C \frac{dV(t)}{dt}[/tex]

If you can only drive 10nA, that will limit how fast your circuit can run.

 

[ZeroFunGame]

So then there is no fundamental lower limit to Ion/Ioff for logic applications if switching speed was not an issue?

 

[berkeman]

So then there is no fundamental lower limit to Ion/Ioff for logic applications if switching speed was not an issue?

Switching speed is an issue in every practical circuit application that comes to mind for me.

Do you have an application in mind, or is this just a strange thought experiment?

 

[ZeroFunGame]

Switching speed is an issue in every practical circuit application that comes to mind for me.

Do you have an application in mind, or is this just a strange thought experiment?

It's a thought experiment. Trying to tease out the fundamental limitations rather than setting an application and then deriving the specifications. It's much easier to derive targets from a platform, but this hides the fundamental limitations in the underlying technology

 

[berkeman]

It's a thought experiment. Trying to tease out the fundamental limitations rather than setting an application and then deriving the specifications. It's much easier to derive targets from a platform, but this hides the fundamental limitations in the underlying technology

So here is a simple CMOS building block. Can you say a bit about what it is, and what it is used for? Also, as you lower the Ion value closer to the leakage current Ileak, what kinds of limiting factors can you envision? (assuming very slow operation like you were asking about)

https://www.tutorialspoint.com/vlsi_design/images/implementation_of_clocked_nor.jpg

 

[trurle]

Yes, I meant to say Ion/Ioff ratio.

For example, can logic circuits be built with an Ion/Ioff ratio of 1000? 100? 10? 2?

Where is the limit and why? Is there a rule of thumb? Trying to understand if there's a quantitative rational for a minimum Ion/Ioff ratio

Old IIC logic family had on/off current ratios of about 3000. This is at lower limits of practical highly integrated circuits. Modern low-voltage CMOS operating around 0.8V power supply voltage typically have on-off ratio about 10000.
Yes, this is mostly rule of thumb. Typically with more switches maximal parameter deviation increase, eroding on/off margin. In modern CMOS the problem with parameters variation may happen not only with transistors, but also with tungsten contacts to metal lines (which are actually smallest part of transistor - smaller than even gate)