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phyzguy said:It's an SR NOR latch - the schematic is shown at this site. Are you familiar with MOS transistors at all? If not, this youtube tutorial should explain the basics. In this layout, the following colors are used:
Red - Poly gate
Orange - P+ Diffusion
Green - N+ Diffusion
Blue - Metal-1
Filled Aqua squares - contacts that connect the Metal-1 to the poly and diffusion layers.
Try tracing out the layout and matching it to the schematic of the SR latch. If you have more questions, ask!
analogdesign said:Phyzguy is right. This latch would be used, for example, as the sense amp in an SRAM.
Tracing it out is the way to go. Start by following the gates (red lines) and see where they cross diffusions to create transistors. Keeping in mind that two devices often share a diffusion.
Also, the dotted blue line around the top devices is a N-Well. This is a p-substrate process (I know that because the nmos devices on the bottom of the layout are implemented in the substrate and not in a well).
The square near the VDD label is a well contact and the square near the GND label is a substrate contact. These are needed to reduce the resistance between the circuit and the well/substrate to mitigate latch-up.
Good luck! This is a good circuit to get started on!
analogdesign said:I think you got it! Good job. Try to draw it a bit more in the standard way and how it works will be more clear to you.
phyzguy said:Looks good to me, too. You might try learning how to use a schematic editor to draw the schematics. There are several free open-source ones to choose from.
dafaq said:please tell me the names..i will download and start working on them... i have access to cadence in my uni but that i am absolutely noob at (maybe i will be able to handle it by the end of this term)!
sandy.bridge said:Question: does one require a good background in digital electronics to do this type of design? There is a graduate class at my university that offers a course in this, but the description never indicated that such was necessary.
dafaq said::) if its not a big trouble then can u please show me the standard model of it ? i want to compare and learn .. a hand drawn one like me will be good enough...
EDIT: please have a look at it.. is this how the standard diagram should be?
phyzguy said:If you have access to Cadence, you should use that. Everyone starts off as a beginner. Try entering the schematic you drew, and then you will be less of a beginner.
analogdesign said:Looks good! You got it.
I agree 100% if you have Cadence Virtuoso use it. It completely dominates the industry. I have it open in another window right now. :)
dafaq said:thank you both for helping me :) seems like you guys are professionals in this field :) (one doesn't simply keeps cadence open in next window :D )
one last question - how did you guys know it was SR (nor)latch? is it pure experience or there's some technique to quickly understand the underlying functions ?
meBigGuy said:I one had a picture of me drawn on a chip (long story). One company I worked with had a policy against signing chips so the designers put their initials in metal with voltages such that it would show up on an e-beam prober.
Cadence has a steep learning curve in that you have to almost be an expert to do anything. Don't let that frustrate you since the end result is a very rich toolset. Just pray you never have to learn their SKILL programming language.
dafaq said:one last question - how did you guys know it was SR (nor)latch? is it pure experience or there's some technique to quickly understand the underlying functions ?
dafaq said:bigguys :) here is my first input, please correct me if i am wrong ---
dafaq said:@phyzguy: i think the PUN is implementing (B+S).(A+S')
is it so?
dafaq said:@phyzguy
i made the truth table.. have a look.. but i can't really match this with something i remember.. can you please remind me? :( besides, what will be the worst case delay input transition ?