Doing a HNC course and my current module is hydraulics and pneumatics. Never done this before so not sure if my thinking is correct for this question. The handouts are a bit vague in places and I can't find anything relevant on the net.
1. Homework Statement
What problems may occur if a...
I know, it's a weird one. My old notes from college days has a big 'this is the problem with the SR bistable' part, but absolutely nothing for D-type, and getting nothing on internet search about it.
Well, I don't have to list them versus each other, just give an example of a disadvantage of each one by itself. IE - the SR has the indeterminate state. Could you say the fact the D has only one 'input' be classed as a disadvantage in itself? Obviously if you needed more than one input you...
It's information for a work briefing project. Doesn't have to be too technical (hence why I don't need anything for delay propagation or such) as it's for non-techys. I've just got to list a general disadvantage of the D-type bistable (latch or FF). Can't find anything online that has any of...
Can anyone think of big disadvantage of D-type bistables, without having to go into propagation delay/rise times and stuff like that? I'm thinking for something along the lines of the S-R flipflop and it's indeterminate state on a 1 - 1 input. The only thing I can think of myself is if we get...
It's just taking the inputs of a single bit full adder and putting in the connections to give the sum and carry outputs. I've taken some of the connections off as I've worked them out and don't want to be accused of cheating. All I need to know is if I need to put the extra connections to either...
Hi all, quick question about a PLA circuit I'm doing for coursework. I'll upload a pic of the circuit to help explain. I've got the main stuff worked out but a little line in the coursework is making me think if I need to add a couple of extra connections on it. The circuit has 7 incrementing...
Not sure if this is in the right thread for this, but it is related to a question I'm doing.
1. Homework Statement
I've been tasked with realising a logic circuit that has 3 inputs and 2 outputs which have separate Boolean equations. The circuit is based around a LS153, 1 of 4 multiplexer...
Sorry I haven't posted back...forgot all about this post. I got it right in the end, Instructor said I could prove it however I wanted, so I just drew various combinations of 3-4 gates and their associated logic.
Hi guys, got a question that's got me stumped. Not looking for the answer as I'd prefer to work it out myself, just a nudge or a pointer in the right direction.
I'm being asked to prove if an XOR gate can be classed as universal (like the NAND & NOR gates are), but not sure how to go about it. I...
I've worked further and managed to get to the point where
V_o(s) = \frac{100}{s} - \frac{100 s}{s^2 + 10 s + 2000} - \frac{1000}{s^2 + 10 s + 2000}
The next line has me stumped a bit tho. I'm not sure if this is even the right way to go, but I can't seem to factorise it normally. It...
I think I realized where I went wrong...I was on autopilot and instead of dividing num and den by 'R', I simply canceled them out, so there no way it was going to work.
Working past that I got to 100Vi/s(Ls/R + s^3LC + s)
Working out 100vi/LCs(s^2+s(1/RC)+1/LC gives my above line (I hope) so...
Thanks for the replies...I realized where I went wrong suddenly, ie- had to make it 'standard form' and needed a 1 on the numerator instead of the 0.641...so manipulated the equation and it all fell into place.
So once again, thankyou all for the help.