A 5-stage DLX pipelined processor is equipped with the
forwarding technique. The following code is executed in the
processor.
XOR R5, R5, R6 //R5=R5 XOR R6 (XOR: logic operation)
LW R1, 20(R5) //load word into R1
ADDI R1, R1, #2 //increment R1 by 2
SW 20(R5), R1 //store the content in R1 to...