Pipeline Stalls and Reassigning Registers

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In summary: So Z has to be in a register in bank B. So Y and Z have to be in different banks but this is not doable so a conflict occurs. Upon further reading notes it states registers need to always be on different banks. It states you cannot add two numbers from the same bank because there would be no way to access them from the same adder. In summary, there are three pipeline stalls at Line 6, four stalls at Line 10, and three stalls at Line 11. To avoid register conflicts, both Line 8 and Line 10 would need to be changed since they are adding two registers from the same bank. This can be done by switching one register for another from the other bank.
  • #1
ver_mathstats
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Homework Statement
Given the code count the pipeline stalls and reassign register numbers to avoid register conflicts (anything after "#" is a comment):
Line 1: load r0, 10 # load value 10 into register r0
Line 2: load r1, 1 # load immediate value 1 into r1
Line 3: load r2, 0 # load 0 into r2
Line 4: load r3, 0 # load 0 into r3
Line 5: load r4, 1 # load 1 into r4
Line 6: load r5, 0 # load 5 into r5
Line 7: while :
Line 8: add r1, r2 # add contents of r1 and r2, store into r2
Line 9: mov r4, r5 # r5=r4
Line 10: add r3, r4 # r4 = r3+r4
Line 11: mov r5, r3 # r3=r5
Line 12: cmp r2, r0 # cmp = r2>=r0
Line 13: bne while

<mentor edit>
Some background information is that bank 1 has registers r0-r3 and bank 2 has registers r4-r7, and add means addition, mov means moves a value from one register to another, cmp means the comparison of two values, bne increments the program counter pc by an immediate value if the value of the global register cmp is not equal to 1. This is also a five-stage pipeline.
Relevant Equations
pipeline stalls, reassigning registers
These questions really confuse me so I am really unsure if I am doing this correctly. For the pipeline stalls I have gathered that there is a stall "Line 9: mov r4, r5 # r5=r4" since "Line 6: load r5, 0 # load 5 into r5" contains r5, meaning there would be two stalls. Another stall at "Line 10: add r3, r4 # r4 = r3+r4" because just in the previous line there is r4, meaning there is four stalls here. Then "Line 11: mov r5, r3 # r3=r5" stalls because there is r5 in "Line 9: mov r4, r5 # r5=r4" meaning there would be three stalls here. Would "Line 12: cmp r2, r0 # cmp = r2>=r0" stall because of "Line 8: add r1, r2 # add contents of r1 and r2, store into r2"? I presume it would not just because of the other stalls previously mentioned. This was just the first run, the while loop will happen an additional 10 times until r2>=r0 meaning we total the loops for the first run and multiply by 11.

For reassigning register numbers I was reading my textbook which gave: X←X+Y, S←Z-X, T←Y+Z, it had explained that to perform the first addition we require X and Y must be in separate register banks, meaning X is in the register in bank A and Y is in a register in bank B. Then it explained Z must be in the opposite register bank than X. So Z has to be in a register in bank B. So Y and Z have to be in different banks but this is not doable so a conflict occurs. Upon further reading notes it states registers need to always be on different banks. It states you cannot add two numbers from the same bank because there would be no way to access them from the same adder.

Based on this information then I am guessing we would have to change both line 8 and line 10 since they are adding two registers from the same bank, but how would I proceed with this? Would I just switch one register for another from the other bank?

If anyone could check over what I have so far for my work that would be appreciated, thank you.
 
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  • #2
ver_mathstats said:
Homework Statement:: Given the code count the pipeline stalls and reassign register numbers to avoid register conflicts (anything after "#" is a comment):
Line 1: load r0, 10 # load value 10 into register r0
Line 2: load r1, 1 # load immediate value 1 into r1
Line 3: load r2, 0 # load 0 into r2
Line 4: load r3, 0 # load 0 into r3
Line 5: load r4, 1 # load 1 into r4
Line 6: load r5, 0 # load 5 into r5
Line 7: while :
Line 8: add r1, r2 # add contents of r1 and r2, store into r2
Line 9: mov r4, r5 # r5=r4
Line 10: add r3, r4 # r4 = r3+r4
Line 11: mov r5, r3 # r3=r5
Line 12: cmp r2, r0 # cmp = r2>=r0
Line 13: bne while

<mentor edit>
Some background information is that bank 1 has registers r0-r3 and bank 2 has registers r4-r7, and add means addition, mov means moves a value from one register to another, cmp means the comparison of two values, bne increments the program counter pc by an immediate value if the value of the global register cmp is not equal to 1. This is also a five-stage pipeline.
Relevant Equations:: pipeline stalls, reassigning registers

These questions really confuse me so I am really unsure if I am doing this correctly. For the pipeline stalls I have gathered that there is a stall "Line 9: mov r4, r5 # r5=r4" since "Line 6: load r5, 0 # load 5 into r5" contains r5, meaning there would be two stalls. Another stall at "Line 10: add r3, r4 # r4 = r3+r4" because just in the previous line there is r4, meaning there is four stalls here. Then "Line 11: mov r5, r3 # r3=r5" stalls because there is r5 in "Line 9: mov r4, r5 # r5=r4" meaning there would be three stalls here. Would "Line 12: cmp r2, r0 # cmp = r2>=r0" stall because of "Line 8: add r1, r2 # add contents of r1 and r2, store into r2"? I presume it would not just because of the other stalls previously mentioned. This was just the first run, the while loop will happen an additional 10 times until r2>=r0 meaning we total the loops for the first run and multiply by 11.

For reassigning register numbers I was reading my textbook which gave: X←X+Y, S←Z-X, T←Y+Z, it had explained that to perform the first addition we require X and Y must be in separate register banks, meaning X is in the register in bank A and Y is in a register in bank B. Then it explained Z must be in the opposite register bank than X. So Z has to be in a register in bank B. So Y and Z have to be in different banks but this is not doable so a conflict occurs. Upon further reading notes it states registers need to always be on different banks. It states you cannot add two numbers from the same bank because there would be no way to access them from the same adder.

Based on this information then I am guessing we would have to change both line 8 and line 10 since they are adding two registers from the same bank, but how would I proceed with this? Would I just switch one register for another from the other bank?

If anyone could check over what I have so far for my work that would be appreciated, thank you.
I'm not sure what relevance banks play here. More relevant, I believe, is when a register is being operated on in one stage at the same time it needs to be read from or written to by another instruction.
My advice is to make some drawings of how a sequence of instructions progress through the five-stage pipeline. Your text or class notes should (?) show some examples of this.

BTW, your explanation of the meaning of BNE is almost certainly wrong. It should be branch if the value in the noted register is not zero.
 
  • #3
Mark44 said:
BTW, your explanation of the meaning of BNE is almost certainly wrong. It should be branch if the value in the noted register is not zero.
I would guess that BNE means "Branch if the Equal flag is Not set". The equal flag will be set according to the previous CMP instruction (which is also almost certainly described incorrectly). So the code in lines 12 and 13 will branch to the label "while" if r2 is not equal to r0.
 
  • #5
pbuk said:
I would guess that BNE means "Branch if the Equal flag is Not set". The equal flag will be set according to the previous CMP instruction (which is also almost certainly described incorrectly). So the code in lines 12 and 13 will branch to the label "while" if r2 is not equal to r0.
Or IOW, if r2 - r0 != 0.
 
  • #6
Mark44 said:
Or IOW, if r2 - r0 != 0.
Yes, but 0 is not the value in any register!
 
  • #7
pbuk said:
Yes, but 0 is not the value in any register!
I guess I was conflating bne with the corresponding x86 jump instruction. In any case, my comment about 1 vs. 0 was still appropriate.
 
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1. What are pipeline stalls and why do they occur?

Pipeline stalls refer to a delay in the execution of instructions in a computer's pipeline. They occur when there is a dependency between instructions, meaning that one instruction cannot be executed until the previous one is completed.

2. How do pipeline stalls affect the performance of a computer?

Pipeline stalls can significantly impact the performance of a computer by slowing down the execution of instructions and reducing the overall throughput of the system. This can result in longer processing times and lower efficiency.

3. What is the role of reassigning registers in reducing pipeline stalls?

Reassigning registers is a technique used to minimize pipeline stalls by freeing up registers that are no longer needed for a particular instruction. This allows the next instruction to be executed without waiting for the previous one to finish.

4. Can pipeline stalls be completely eliminated?

No, pipeline stalls cannot be completely eliminated as they are an inherent part of the pipeline design. However, they can be reduced through techniques such as instruction reordering, register renaming, and branch prediction.

5. How do modern processors handle pipeline stalls?

Modern processors use advanced techniques such as out-of-order execution and speculative execution to mitigate the impact of pipeline stalls. These techniques allow instructions to be executed in parallel, reducing the effects of dependencies and improving overall performance.

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