LSM303AGRTR Footprint: DRC Issues and Solutions

[Yoyo G]

Hello everyone!
I hope you're all doing well.
I've been working on a PCB using the LCSC library's LSM303AGRTR. My DRC stalls on the fact that the pad space is insufficient when I try to make Gerber files.
The DRC check generates no issues when I drop the DRC value to 0.5mil. However, a closer examination of the datasheet and footprint reveals that the pad size of this component differs from what is stated in the datasheet. Has anyone had success with this footprint/library part?
Thank you very much in advance!

 

[berkeman]

Hello everyone!
I hope you're all doing well.
I've been working on a PCB using the LCSC library's LSM303AGRTR. My DRC stalls on the fact that the pad space is insufficient when I try to make Gerber files.
The DRC check generates no issues when I drop the DRC value to 0.5mil. However, a closer examination of the datasheet and footprint reveals that the pad size of this component differs from what is stated in the datasheet. Has anyone had success with this footprint/library part?
Thank you very much in advance!

The recommended pad size will generally be a little larger than the actual IC pins or balls, to improve solderability. Is that the mismatch you are concerned about?

You should get the design rules from your PCB Fab House -- they may use different design rules for different processes that they have available (more expensive for smaller feature size DRC values)

 

[Rive]

I've been working on a PCB using the LCSC library's LSM303AGRTR. My DRC stalls on the fact that the pad space is insufficient when I try to make Gerber files.

You are supposed to set (modify) the DRC rules according to the project requirements // PCB manufacturer capabilities. The default rules are usually just 'mostly OK' and cannot correctly handle special requirements/parts.

 

[Joshy]

DRC value of 0.5 mil is basically nothing. It's 12.7 um. Unless you're working on IC packaging that number is probably not achievable by a lot of places, and even there I would think it's uncommon. Speaking of mils versus microns... check your units. I'm pretty sure it would be obvious once you place the part, but it's worth mentioning and checking since it's easy and I'm not sure what new people would/n't notice.

^ Advice above is pretty good. Work with the fab house to get the numbers you need.

Footprint not matching an application note is not going to trigger DRCs. A lot of footprints don't really match the application notes because of tolerances. If you design to the nominal value, then you're going to be in big trouble when parts come in and they are a little bit bigger or smaller. Some guidelines I've seen... such as IPC... do not match the footprint. You'll notice things like longer and more narrow pads. All of the tools I've worked with also have an extra checkbox or property that allows some component specific DRCs to be automatically waived (ie. pin to pin clearance).

A lot of people do not do the layout with the soldermask layer showing (totally okay), but this layer causes a lot of DRCs. They'll put the soldermask expansion on their pins and place them closely together... you'll have small soldermask slivers and webs, which a lot of fab houses do not like. It would not surprise me if the default rules had a check for it. A quick fix for this is to gang relieve these pins, which is just a big soldermask cutout enclosing the pins that are close to each other. This can come with it's own can of worms related to assembly risks, but you'll want to communicate with the fab house to understand those risk and determine what's right for you.