Latch to quick 3V signal with SR latch

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In summary, the conversation discusses using a SR latch or flip flop to create an external latch circuit for a quick 3V signal that needs to be recorded by a slow sampling DAQ. There is a potential race condition that can be addressed by using two latches and sampling/clearing them separately.
  • #1
pegasixi
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I'm a beginner at electronics, so please bear with me...

I have a 3V signal that is triggered under a certain condition and stays on for less than a second (I have no control over this). This is connected to a DAQ that can only sample at very slow rates (Also, no control over this). I'm trying to build a quick and dirty external latch circuit that will allow me to register this quick 3V signal and then "latch" on to it so that it can be registered by the DAQ (which samples at 1 sample per minute more or less)

My idea is to use a SR latch with the SET connected to a lead that connects to the terminal that outputs the momentary 3V signal and the RESET connected to any low voltage source. This way, when the 3V signal goes off, it will be latched to 3V and be able to be recorded by the DAQ when it finally gets around to sampling it.

Am I on the right track? Thank you.
 
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  • #2
pegasixi said:
I'm a beginner at electronics, so please bear with me...

I have a 3V signal that is triggered under a certain condition and stays on for less than a second (I have no control over this). This is connected to a DAQ that can only sample at very slow rates (Also, no control over this). I'm trying to build a quick and dirty external latch circuit that will allow me to register this quick 3V signal and then "latch" on to it so that it can be registered by the DAQ (which samples at 1 sample per minute more or less)

My idea is to use a SR latch with the SET connected to a lead that connects to the terminal that outputs the momentary 3V signal and the RESET connected to any low voltage source. This way, when the 3V signal goes off, it will be latched to 3V and be able to be recorded by the DAQ when it finally gets around to sampling it.

Am I on the right track? Thank you.

Welcome to the PF.

Yep, that's the way to do it. You can use an SR latch or some variant of a flip flop. The DAC unit should clear the latch at the start of everything, and clear it after it has read the high value.

You could get into a little bit of a race condition where the DAC is clearing the latch at the same time as the signal is coming in. If this is an issue, you could use two latches both watching for the incoming signal, and sample/clear them separately at slightly different times from the DAC unit.
 

Related to Latch to quick 3V signal with SR latch

1. What is a latch to quick 3V signal with SR latch?

A latch to quick 3V signal with SR latch is a type of electronic circuit that stores and remembers a 3V signal. It uses a set-reset (SR) latch to hold the signal in place until it is reset.

2. How does a latch to quick 3V signal with SR latch work?

The SR latch has two inputs: S (set) and R (reset). When the S input is set to 1, the output will also be set to 1. When the R input is set to 1, the output will be reset to 0. This allows the latch to store a 3V signal until it is reset by the R input.

3. What are the advantages of using a latch to quick 3V signal with SR latch?

One advantage is that it is a simple and efficient way to store a 3V signal without the need for external components. It also allows for quick and easy retrieval of the signal when needed.

4. What are some common applications of a latch to quick 3V signal with SR latch?

This type of latch is commonly used in electronic devices to hold and remember a specific voltage level. It is also used in control systems to store a signal and trigger an action when the signal is released.

5. Are there any limitations to using a latch to quick 3V signal with SR latch?

One limitation is that the signal can only be stored for a limited amount of time before it needs to be refreshed. Additionally, if the inputs are not properly controlled, it can result in unstable output states.

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