P-channel SiC MOSFET was developed only recently (in 2017). Previous models of integrated SiC chips have used N-channel MOSFETonly, and N-channel only architectures do limits integration to roughly 80386 levels (<1 mln. transistors), because of associated high power dissipation.ZeroFunGame said:Summary: There has been a demonstration of SiC BJT ACDs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?
There has been a demonstration of SiC BJT ADCs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?
trurle said:P-channel SiC MOSFET was developed only recently (in 2017). Previous models of integrated SiC chips have used N-channel MOSFETonly, and N-channel only architectures do limits integration to roughly 80386 levels (<1 mln. transistors), because of associated high power dissipation.
https://powerelectronicsworld.net/article/101899/Making_A_Debut_The_P-type_SiC_MOSFET/feature
trurle said:P-channel SiC MOSFET was developed only recently (in 2017).
All highly integrated ICs today are based on CMOS MOSFETs, not BJTs or JFETs. As @trurle pointed out, until we have good NMOS and PMOS transistors in SiC, you will not see the kind of "100's of million transistor +" levels of integration that you are used to with Si CMOS. Even then, there are probably many processing techniques that have been developed to work with Si that, for one reason or another, don't work with SiC. It will take time to develop the new methods. And I'm not sure what the financial motivation is. It's true there are markets (high-temperature, for example) where SiC outperforms Si. But is this more than a niche market? Is the market large enough to give the developers incentive to switch from Si?ZeroFunGame said:Summary: There has been a demonstration of SiC BJT ACDs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?
There has been a demonstration of SiC BJT ADCs, and SiC JFET SRAM. What would be the major limitations associated with higher forms of integration for SiC? For example, a 1billion transistor CPU based on SiC?
phyzguy said:As @trurle pointed out, until we have good NMOS and PMOS transistors in SiC, you will not see the kind of "100's of million transistor +" levels of integration that you are used to with Si CMOS.
berkeman said:Links please?
I am not even sure the leaflet of 2017 can be counted as "useful SiC CMOS process", not even speaking of research paper in 1997. Current digikey.com inventory of p-channel SiC MOSFETs is 3 positions with 1 device variety (while over a thousand of N-channel SiC MOSFETs).ZeroFunGame said:Also, I'm not sure SiC PMOS was only developed in 2017 -- here's a SiC CMOS demonstration in 1997
https://ieeexplore.ieee.org/abstract/document/568759
Because N-type VLSI have a significant stand-by power independent of transistor width (and reverse proportional to gate length), Si NMOS process did run in thermal troubles as soon as each transistor active area (channel+drain+source) was shrinked to roughly 4um2 size. With practical transistors active area density 15% in digital chips, 1mln transistors chip would be 5x5mm size, which is close to maximally practical with respect to cost.ZeroFunGame said:Thanks trurle! Very insightful! I was curious how the 80386 levels was concluded? I wondering because, if power/efficiency was not a design spec, then would it follow that >1 mln. transistor systems are achievable? Or are there fundamental limitations to n-type VLSI?
trurle said:I am not even sure the leaflet of 2017 can be counted as "useful SiC CMOS process", not even speaking of research paper in 1997. Current digikey.com inventory of p-channel SiC MOSFETs is 3 positions with 1 device variety (while over a thousand of N-channel SiC MOSFETs).
trurle said:which is close to maximally practical with respect to cost.
A SiC (silicon carbide) microprocessor is a type of microprocessor that uses silicon carbide as the semiconductor material instead of traditional silicon. This allows for higher performance and efficiency due to the unique properties of SiC.
The main limitation of integrating SiC into a microprocessor is the high cost of production. SiC is a relatively new and expensive material, making it difficult to mass produce SiC microprocessors at a competitive price. Additionally, the manufacturing process for SiC is more complex and requires specialized equipment, further driving up the cost.
SiC has a higher breakdown voltage, higher thermal conductivity, and higher electron mobility compared to traditional silicon. This allows for faster switching speeds and higher power handling capabilities, resulting in improved performance in microprocessors.
Another limitation of SiC integration is the lack of standardization. Unlike silicon, which has well-established manufacturing processes and standards, SiC is still in the early stages of development and lacks standardization. This can make it difficult for manufacturers to produce SiC microprocessors that are compatible with existing systems and technologies.
The potential benefits of using SiC microprocessors include higher performance, improved energy efficiency, and the ability to operate at higher temperatures. SiC also has a longer lifespan and is more resistant to radiation and other environmental factors, making it a promising material for use in critical applications such as aerospace and defense.