- #1
imixerik
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- Homework Statement
- Consider a system that can host 64 GB of memory and has 8MB of L3 cache. Suppose that each cache line contains 4 chunks, each of size 16B.
a) Assuming 4-way associative cache, what are the lengths (in bits) of the following: tag, cache index, and block offset?
b) How does this change for a 2-way cache?
c) Suppose that if L3 is organized as 2-way, the access time is 20 cycles, but increases to 22 cycles if organized as 4-way, but the miss probability from L3 decrease from 12% to 10%. Suppose that the misses from L3 go to memory, and the average memory latency is 64 cycles. State which option is better and why.
d) Now suppose that the L2 cache can be organized as direct map or 4-way. In the first case, the L2 limited CPI (i.e., CPI if there is no miss out of L2) is 3.5 and MPI out of L2 is 0.08. In the second case, the CPI increases to 3.8 but the MPI is 0.06. Determine the best configuration for this system by considering all four possibilities: (i) DM L2, 2-way L3, (ii) DM L2, 4-way L3, (iii) 4-way L2, 2-way L3, and (iv) 4-way L2, 4-way L3.
- Relevant Equations
- Not sure what equations to use
Have been trying to figure out this problem for quite some time but don't know how to approach it.