Gate driving voltage for GaN MOSFETS

[Ntip]

TL;DR Summary

Is negative gate voltage required for GaN MOSFETS?

I am interested in using GaN MOSFETS for my circuit and I'm looking at the EPC2012C. I'll attach the datasheet here. I noticed that it calls for a -4 Vgs. If my driver only goes to 0 V, will this cause a problem? What is the benefit in driving negative if it's not required?

 

[berkeman]

Summary:: Is negative gate voltage required for GaN MOSFETS?

EPC2012C

https://epc-co.com/epc/Portals/0/epc/documents/datasheets/EPC2012C_datasheet.pdf

That looks to be the lower limit of the Absolute Max Ratings...

Maybe check out the other characteristics in the datasheet, like this one:

 

[Ntip]

https://epc-co.com/epc/Portals/0/epc/documents/datasheets/EPC2012C_datasheet.pdf

That looks to be the lower limit of the Absolute Max Ratings...

View attachment 276679
Maybe check out the other characteristics in the datasheet, like this one:

View attachment 276680

It looks like that plot shows Rds for turnon voltage so I can see that going to +5 Vgv on gives lower Vgs than say 3.5 V but I don't see a plot or anything discussing turnoff voltage which is negative...(-4 V) at the lowest.

 

[Ntip]

https://epc-co.com/epc/Portals/0/epc/documents/datasheets/EPC2012C_datasheet.pdf

That looks to be the lower limit of the Absolute Max Ratings...

Maybe check out the other characteristics in the datasheet, like this one:

Ok so was looking at IEEE articles on this and should've spent the day switching instead. For a simpler explanation than reading research papers, I found this reference.

https://gansystems.com/wp-content/u...GN001_Design_with_GaN_EHEMT_Rev3_20161007.pdf

 

[DaveE]

A couple of more general points about using semiconductor devices:

1) Device manufacturers really, really, really want you to use their stuff successfully. They also want you to choose their technologies in your initial planning. So... They (the good ones), that are selling newer technologies, spend a bunch of money on applications engineers that will create lots of materials to teach you how to use their stuff. Go there first for information and education. They are engineers, like you, they will be efficient at telling you what you need to know.

2) However, OTOH, a GaN manufacturer won't always be objective about the benefits of Si or SiC, so be aware that they are subtle salesmen. So you will also want to become familiar with the different technologies in a general sense; their benefits, costs, targeted applications, etc. The same is true for general design requirements. For example, we all know (or will) how to drive the gate of a Si MOSFET, except for subtle details, there isn't a need to worry about the details of the different manufacturer's devices. Same for SiC, GaN, etc.

3) Engineers, like you and I, have a weakness, a bias; we are interested in and want to use the newest coolest technologies. If you want to make your management and customers happy, you need to be objective about this. In my 30+ year career, I rarely actually got to do the designs I thought maximized my fun, interest, and education. When looking at newer technologies, make sure that you are objectively evaluating them against the tried and true approaches. New devices are typically targeted at niche applications, or what I might call extreme tech. These are companies that don't worry too much about NRE, time to market, low cost, etc. You also need to match the entire design to the benefits of these devices. For example, there isn't any point in using the latest uP with the best benchmarks, if you don't give enough RAM to allow it to shine. There isn't any point in using the fastest power transistor if it's too fast for it's commutating diode, or if you don't layout your PCB to take advantage of it's speed. SMPS that switch above 1MHz are interesting, feasible, and sometimes a good solution. But, there is a really good reason that most SMPS use Si MOSFETS at 100-200KHz.

edit:
4) Steal the application engineers circuits as much as possible, especially PCB layout snippets. They put a lot of effort into them, effort that you can skip if you take their advice.

 

[Baluncore]

I noticed that it calls for a -4 Vgs. If my driver only goes to 0 V, will this cause a problem? What is the benefit in driving negative if it's not required?

Vgs = -4 V is only during a Gate-to-Source Reverse Leakage test.
With Vgs = zero there may still be some drain current, maybe up to 1 mA.
We need to see your circuit before we can identify the critical parameter.

 

[DaveE]

What is the benefit in driving negative if it's not required?

In some cases there is a benefit in having a gate driver try to drive the gate more negative than the DC curves in the datasheet imply. This is in response to the fact that the actual gate voltage during transitions is a dynamic thing, so "overdriving" sometimes helps. The point isn't that you need the real Vgs to be negative, but that you want it to get to zero faster, or you want it to stay at zero.

The classic problem is the C_dg (Miller) capacitor, which will inject current into the gate during switching due to high dv/dt at the drain. Weak gate drive can make for slow switching because you can't charge the C_dg cap fast enough.

Frankly, I think this is more common in Si devices because they are inherently slower devices (high C_dg). I never really looked at this in GaN devices.

There is a similar problem with source inductance and high di/dt. I recall one app engineer say that GaN TO-220's were pointless because the package had too much inductance in the leads to allow the transistor to switch fast enough.