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- #1

- Thread starter shamieh
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- #1

- Jan 30, 2012

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I am not familiar with Verilog (I am using another software that uses file extension .v ), but I don't understand "f(~y&~x)". Since there is no operator between f and (~y&~x), it looks like a function application, but f has not been declared a function (this requires the "function" keyword). I tried to compile this code on www.compileonline.com, and it seems to say the same thing:Module test1(f,g,x,y,z);

input x,y,z;

output f,g;

assign g = f(~y&~x);

assign f = x&y | ~x&z;

endmodule;

Code:

```
main.v:5: error: No function f in this context (test1).
main.v:5: error: Unable to elaborate r-value: f((~(y))&(~(x)))
```

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I got mine to compile fine. It was a typo on my part originally i put a semicolon at the end which was wrong, but if you copy and paste this in the compiler you just linked me, it compiles and executes fine. But how do I actually draw this monster? Here is the code that will compile below if you want to try for yourself.I am not familiar with Verilog (I am using another software that uses file extension .v ), but I don't understand "f(~y&~x)". Since there is no operator between f and (~y&~x), it looks like a function application, but f has not been declared a function (this requires the "function" keyword). I tried to compile this code on www.compileonline.com, and it seems to say the same thing:

Besides, "module" in Verilog is written with a lowercase m and apparently there should not be a semicolon after "endmodule". If you want to design circuits, you have to be extra careful about such things.Code:`main.v:5: error: No function f in this context (test1). main.v:5: error: Unable to elaborate r-value: f((~(y))&(~(x)))`

Code:

```
module test1(f,g,x,y,z);
input x,y,z;
output f,g;
assign g = f|(~y&~x);
assign f = x&y|~x&z;
endmodule
```

- Jan 30, 2012

- 2,512

This makes a big difference because now there is an OR after f. So f is not a function, but a regular variable. Before, even if f had been declared a function using the "function" keyword, it would have been unclear how f, which depends on two inputs x and y, can be applied to a single argument (~y&~x).Code:`module test1(f,g,x,y,z); input x,y,z; output f,g; assign g = f|(~y&~x); assign f = x&y|~x&z; endmodule`

If you understand the order of evaluation, drawing a circuit is easy.

(1) x and y go to an AND

(2) x gets inverted and with z goes to an AND

(3) outputs of (1) and (2) go to an OR

(4) y and x get inverted and to to an AND

(5) outputs of (3) and (4) go to an OR.