- Thread starter
- #1
I am not familiar with Verilog (I am using another software that uses file extension .vModule test1(f,g,x,y,z);
input x,y,z;
output f,g;
assign g = f(~y&~x);
assign f = x&y | ~x&z;
endmodule;
main.v:5: error: No function f in this context (test1).
main.v:5: error: Unable to elaborate r-value: f((~(y))&(~(x)))
I got mine to compile fine. It was a typo on my part originally i put a semicolon at the end which was wrong, but if you copy and paste this in the compiler you just linked me, it compiles and executes fine. But how do I actually draw this monster?I am not familiar with Verilog (I am using another software that uses file extension .v), but I don't understand "f(~y&~x)". Since there is no operator between f and (~y&~x), it looks like a function application, but f has not been declared a function (this requires the "function" keyword). I tried to compile this code on www.compileonline.com, and it seems to say the same thing:
Besides, "module" in Verilog is written with a lowercase m and apparently there should not be a semicolon after "endmodule". If you want to design circuits, you have to be extra careful about such things.Code:main.v:5: error: No function f in this context (test1). main.v:5: error: Unable to elaborate r-value: f((~(y))&(~(x)))
module test1(f,g,x,y,z);
input x,y,z;
output f,g;
assign g = f|(~y&~x);
assign f = x&y|~x&z;
endmodule
This makes a big difference because now there is an OR after f. So f is not a function, but a regular variable. Before, even if f had been declared a function using the "function" keyword, it would have been unclear how f, which depends on two inputs x and y, can be applied to a single argument (~y&~x).Code:module test1(f,g,x,y,z); input x,y,z; output f,g; assign g = f|(~y&~x); assign f = x&y|~x&z; endmodule