Digital Ramp ADC Analysis difficulty

In summary, the conversation is discussing an assignment involving circuit analysis for a fuel level meter. The task is to analyze a circuit that converts an analog voltage into a binary number to be displayed on a 7 segment display. The conversation includes discussions on calculating suitable resistances for the circuit, understanding the role of op-amps in the circuit, and determining the binary value that will appear at the outputs of the register for a given voltage.
  • #1
jf623
10
0
I'm trying this problem on allaboutcircuits too. However they havn't been as helpful as this board is for other problems (mostly mathematics).

Homework Statement


I have been given an assignment which is part of, what I consider, the most difficult part of electronics engineering. Circuit analysis. It is to analyse the attached circuit, which is a fuel level meter for a car. It is a design for an ADC to convert an analogue voltage (v_fuel) ranging from 0 to 3V (3V being a full tank) into a 4 bit binary number, which is then sent to a 7 segment display.

(a) Calculate suitable resistances for R1 to R5 so that the binary values from the counter produce voltages from 0 V to approximately 3.75 V in approximately 0.25 V steps at point K in the circuit.

(b) Explain and sketch graphs of what is happening at points J, K, L.

Homework Equations


Resistors R1 to R4 are related in that R3=2*R4, R2=2*R3, R1=2*R2.
OA1, OA2, OA3 are all HCT logic family op-amps (TL074).
Vp = 5V, Vm = -5V.


The Attempt at a Solution


I understand that the resistor network, and, OA1, OA2, OA3 are all together a DAC. OA2 is simply inverting and isolating, OA3 is definitely a comparator and I understand that more than any other part. I know OA1 is a summing amplifier, but I am uncertain how it relates to the resistor network. I think that it is shifting the voltage range from 0V -> 5V, to 0V -> 3.75V. I am having extreme difficulty approaching this problem, I have all the lecture notes and books on this topic. Should I treat the summing amplifier as an inverting negative feedback op-amp, and find a fractional gain of it, then apply the descending values of resistance? (b) should be straightforward once I understand (a).
 

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  • #2
The counter and the opamps are there to generate a stepped ramp which rises to eventually equal the fuel gauge voltage. This causes the current value of the counter to be loaded into the register.

You could start by assuming all the outputs of the counter are high. This puts all the resistors (R1 to R4) in parallel, with 5 volts on one side of them and an opamp input on the other.

Now, work out the size of the resistor which would give the required voltage at point J.

This is the combined parallel resistance of R1 to R4. You know their relationships to each other so you can work out the value of each of them.
 
  • #3
As you know, the resistors are in the ratio R (MSB), 2R, 4R, 8R. To get actual values you will therefore need to decide the value of R. What are the constraints?

The value of R must not be too small, or the counter outputs would be heavily loaded: this could do damage, or at least make the output voltages droop, leading to inaccuracy. The total current with all bits high must also be less than the maximum available from OA1, when delivering the required -3.75V into 10kohms load.

The resistances should not be arbitrarily high however, or the speed of operation could be unduly slow. Errors due to bias current and leakage would also increase. At a guess, R of the order of tens of k ohms might be suitable, but you should make calculations based on the data for the devices actually used.

In a practical situation with discrete components there would also be the issue of preferred values, but possibly this is not necessary for your assignment.
 
  • #4
Ah thank you for the help lads, but I had already worked this out. The next problem that has halted me is this:

(e) What binary value will appear at the outputs Q3 to Q0 of the register REG1, when v_fuel is 1.1 V?

All of a sudden the comparator doesn't make sense! I think too much tea and stress is blurring my logic, I'd be grateful if someone can confirm it:

Take Vstep to be the +voltage into the comparator (OA3). Take Vo to be the output from the comparator into the diode.
if Vstep > Vfuel : Vo = -5V therefore '1' at REG1
if step = Vfuel : Vo = 0 therefore '1' at REG1
if step < Vfuel : Vo = +5V therefore '0' at REG1

So if Vstep >= Vfuel, then the shift register moves and stays at '1'. And it will only allow the data through once, as it operates only on the rising clock edge? Is this correct?

So this would mean that when Vfuel = 1.1V, then binary 0100 (3) will appear at Q3 to Q0 on REG1. As step 3 is 1V.
 
  • #5


I can understand your struggle with this problem. Digital Ramp ADC analysis can be challenging, especially when it involves complex circuits like the one you have been given. It is important to have a good understanding of circuit analysis and op-amp principles in order to approach this problem effectively.

To begin, it is helpful to break down the circuit into smaller sections and analyze each section separately. As you mentioned, the resistor network and op-amps are working together as a DAC. You are correct in your understanding of OA2 and OA3, but for OA1, it is acting as a summing amplifier as well as an inverting amplifier. The input voltage, v_fuel, is being summed with a reference voltage of 2.5V (half of Vp) at the non-inverting terminal of OA1. This allows for the shifting of the voltage range from 0V-5V to 0V-3.75V.

In order to calculate suitable resistances for R1-R5, you can approach it by setting up a voltage divider equation for each resistor. Since R3=2*R4, R2=2*R3, and R1=2*R2, you can simplify the equations and solve for the values of R1-R5. It may also be helpful to use the concept of superposition to analyze the circuit and determine the output voltage at point K for different input voltages.

For part (b), you can use the information from part (a) to plot a graph of the output voltage at points J, K, and L. At point J, the output voltage should follow a linear ramp as the input voltage increases, while at point K, the output voltage should have a step-like behavior as it increments by 0.25V. At point L, the output voltage should be constant at 3V for input voltages above 3V.

I hope this explanation helps you in approaching this problem. Remember to take your time and break down the circuit into smaller sections to make it more manageable. Also, don't hesitate to seek help from your classmates, professors, or online resources if needed. Good luck!
 

Related to Digital Ramp ADC Analysis difficulty

Question 1: What is a digital ramp ADC?

A digital ramp ADC is an analog-to-digital converter that uses a digital signal to ramp up and down in voltage to approximate the input signal. It converts the analog signal into a digital output by counting the number of steps the digital signal takes to reach the input voltage.

Question 2: How does a digital ramp ADC work?

A digital ramp ADC works by comparing the input analog signal to a known reference voltage. The digital signal is then ramped up or down until it reaches the input voltage. The number of steps it takes to reach the input voltage is then counted and converted into a digital output.

Question 3: What factors affect the accuracy of a digital ramp ADC?

The accuracy of a digital ramp ADC can be affected by several factors such as the resolution of the digital signal, the stability of the reference voltage, and the linearity of the analog input signal. Temperature and noise can also impact the accuracy of the conversion.

Question 4: What are the advantages of using a digital ramp ADC?

One advantage of a digital ramp ADC is its simplicity and low cost compared to other types of ADCs. It also has a fast conversion rate and can handle a wide range of input voltages, making it suitable for various applications. Additionally, it is less affected by external noise and can provide high accuracy with proper calibration.

Question 5: What are some challenges in analyzing the difficulty of a digital ramp ADC?

One challenge in analyzing the difficulty of a digital ramp ADC is the non-linearity of the analog input signal. The relationship between the input voltage and the number of digital steps may not be linear, making it difficult to accurately measure the conversion error. Additionally, factors such as temperature and noise can also impact the difficulty of the analysis and may require additional calibration and testing.

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