Design a 4:2 priority encoder with active low and enable

[Fatima Hasan]

Homework Statement

Design a 4-2 priority encoder with active low and enable.

Homework Equations

The Attempt at a Solution

Here's my work , but I don't know how to connect the enable input.
Any help would be greatly appreciated !

##A = \overline{I2}+\overline{I3}##

##B=\overline{I3}+I2\overline{I1}##

 

[berkeman]

Homework Statement

Design a 4-2 priority encoder with active low and enable.

Active low what? Active low inputs?

And for an asynchronous circuit, what would an enable do? One function might be to clock the new outputs into output latches, but you would need to expand on the problem statement to be sure...

https://en.wikipedia.org/wiki/Priority_encoder

 

[Fatima Hasan]

Active low inputs?

Yes.

 

[berkeman]

And can you expand on how enable inputs have been used so far in the circuits you've been studying? What are they usually used for? How are they often implemented?

 

[berkeman]

BTW, if you are to use active low inputs, does that mean that the enable input should be active low as well? Right now your truth table has the enable input active high...

 

[Fatima Hasan]

And can you expand on how enable inputs have been used so far in the circuits you've been studying? What are they usually used for? How are they often implemented?

It allows a signal to pass when the control signal is high.
Use 2-input AND gate , one input as the enable and the other one as the control signal.

 

[berkeman]

Well, that can be one use of an asynchronouse enable signal. I guess it's up to what you are covering in class right now. At least for me, and enable signal is used to keep the outputs of a circuit block from transitioning when they should not be changing. For example, depending on the delays in that priority encoder, when the inputs change, the output may not change directly to their new value. They may be scrambled temporarily as the input signals change and the delays through different parts of the circuit present strange code combinations to the later gates. So an enable signal could be used to hold the outputs at their current value until the input circuit is stabilized, and then the enable would gate the new values through to the outputs. You can use transparent latches for such a function, for example.

I'm definitely confused by the truth table saying that the outputs are don't cares when the enable signal is low, and then the outputs assume their correct values when the enable goes high. It would make more sense to me to say that the outputs held their previous values when the enable is low, and then assume the new output values based on the new inputs when the enable input goes high. That's where the output transparent latch structures would come in. Maybe ask your TA what is wanted for the enable function?

BTW, it looks like your truth table is missing the line where all inputs are = 1. What is the traditional output of a priority encoder with active low inputs when all inputs are high?

 

[Fatima Hasan]

BTW, it looks like your truth table is missing the line where all inputs are = 1. What is the traditional output of a priority encoder with active low inputs when all inputs are high?

The output = XX.

 

[berkeman]

The output = XX.

But you don't have a line where EN=1 and IN=1111...

 

[Fatima Hasan]

I'd definitely confused by the truth table saying that the outputs are don't cares when the enable signal is low, and then the outputs assume their correct values when the enable goes high.

As I know that if the first row is all 1? We don’t put it in the design. And we don't put the enable with the priority encoder. That's why I don't know how to connect the enable when I design the priority encoder.And I am not sure if the “enable” is high or low?
We just use 4 inputs and 2 outputs and design.