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Why is the PC incremented by 4 for superscalar pipelines?

MIPS assembly language
- Jusamyth
- Post #3
- Nov 18, 2004
- Forum: Computing and Technology
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Why is the PC incremented by 4 for superscalar pipelines?

Hello. I need some help with this question involving Pipelines. Any help would definatley be appreciative. Why is the PC (Program Counter) is incremented by 4 for a superscalar pipeline which executes TWO instructions at a time Thanks in Advance!
- Jusamyth
- Thread
- Nov 16, 2004
- Tags
  
  Architecture Computer
- Replies: 4
- Forum: Computing and Technology