I think it's a XOR port for Y and XNOR for Y negate.I don't want to simulate the circuit by a simulator but I want to size (by hand) W/L for NMOS transistors to get a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load on both differential outputs.
I need help for following exercise from Rabaey - Digital Integrated Circuits: A Design Perspective
Size and simulate the circuit (IMAGE BELOW) so that it achieves a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load on both differential outputs. (VDD = 2.5V) Assume A, B and...