Recent content by dlang99099

Based on a few papers I've found on IEEE, that is not quite the case. There will still be coupling between nearby components. The paper I listed above was citing another paper where they said rotating the capacitors 90 degrees reduced the inductance from 89.3 nH to 7.5 nH giving a 90% reduction...

There is a paper titled "A Study of Integration of Parasitic Cancellation Techniques for EMI Filter Design With Discrete Components" that investigated something very similar to what I'm trying to do except there were no analytical equations to show the coupling. I am trying to do something...

I wouldn't be considering the path through the traces. I'm wanted to show how capacitor orientation and their orientation effect the loop inductance. I know how to look at it and tell which one is the better layout in general but I'd like to be able to quantify by how much. Parallel capacitors...

Thanks Berkeman. I will be laying out my circuit later so I do not have a PDF yet. I would like to solve this analytically so I can see the general change different layouts will produce. I could simply create multiple layouts and use FEA like Maxwell Q3D to find best layout but I would like to...

I am trying to show how parasitic inductance is increased or decreased based on coupling between adjacent parallel capacitors. These capacitors are DC link capacitors so I'm not sure if that means it is not time varying and maxwells equations is no longer relevant?