Why is the equation for KVL not -vR + vL = 0 in this RL circuit?

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In summary, the conversation is about a question regarding the derivation of the current with respect to time in source-free RL circuits. The person is confused about the sign convention used and why the equation is not written as -vR + vL = 0. The other person explains that the components are actually in series and uses the direction of the current as the sign convention for vL and vR. They also mention that both elements are in parallel and in series.
  • #1
caesius
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Homework Statement


Not really a problem, but we're learning about source-free RL circuits and the instructor was deriving the current w.r.t time. I've actually seen this derived a few times but one thing has always bothered me.

Looking at this picture recreated from the text

http://homebrew.net.nz/RL.png

The equation dervied from it says:

Ri + vL = 0

which implies vR + vL = 0

but I've always thought that with KVL you simply write down the first sign you hit when tranversing the circuit, i.e., why is the equation not

-vR + vL = 0

Surely since the two components are in parallel the voltage drop across them has to be equal??!

Thanks if anyone can clear up my confusion
 
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  • #2
caesius said:
Surely since the two components are in parallel the voltage drop across them has to be equal??!

They are in series. We want to say that the currents through
L and R are equal. We use this circulating current direction as
our sign convention for vL and vR.
vL +vR = 0
 
  • #3
Since the direction of i is defined opposite to the actual current you'd get with a positive voltage across R, we have

VR = - i R

Equate this expression with VL and see what you get.

p.s. FYI, in this case the two elements are both in parallel (same voltage) and in series (same current).
 

Related to Why is the equation for KVL not -vR + vL = 0 in this RL circuit?

What is KVL?

KVL stands for Kirchhoff's Voltage Law, which is a fundamental principle in circuit analysis that states that the sum of all voltages in a closed loop is equal to zero.

What is an apparent violation of KVL?

An apparent violation of KVL occurs when the sum of voltages in a closed loop does not equal zero. This can happen due to errors in measurement or calculation, or because the circuit is not ideal.

What are some reasons for an apparent violation of KVL?

Some common reasons for an apparent violation of KVL include non-ideal components such as resistors with significant internal resistance, stray capacitance or inductance in the circuit, and measurement errors.

How can an apparent violation of KVL be resolved?

If the violation is due to measurement errors, recalculating or remeasuring the voltages can help resolve the issue. If the circuit is not ideal, taking into account non-ideal components or using more advanced circuit analysis techniques can also help in resolving the apparent violation.

Why is KVL important in circuit analysis?

KVL is important in circuit analysis because it is a fundamental principle that helps in understanding and analyzing circuits. It is used to determine voltage drops, current flows, and other important parameters in a circuit. It also helps in identifying errors and inconsistencies in circuit designs.

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