Homework Statement
Halo, I have written a always@ (code i,pic1) which can output what I want but the result is delayed 1 clock cycle, therefore I have changed it to assign (code ii,pic2)and try to output the recover signal immediately when pcreg_1 is changed. But waveform is not what I wanted...
Homework Statement
Hi, I am now currently working with a CPU. Now I want to write the RAM's MEM into a .txt file.
reg [31:0] mem [ 0 : (32'h0000_5000 / 4)-1 ]
// To .txt
integer test_file;
initial
begin
test_file = $fopen("result_file.txt","w");
end
//the MEM...
Homework Statement
logic [4:0]counter;
logic [WORD_W-1:0] mdr_rite_[counter]; //range must be bounded by constant expressions
logic [WORD_W-OP_W-1:0] mar_rite_[counter]; //range must be bounded by constant expressions
always_ff@(posedge clock, negedge n_reset)
begin
if (!n_reset)...
Thanks for your reply
I am using a simply processor and run it in modelsim using verilog. I want to find out the soft error rate and do the recovery. Before the recovery stage, I need to see which block in the processor cause the most errors rate and then consider how much recovery blocks...
Homework Statement
Hi, I am trying to inject some faults into a CPU manually. But I am not sure what should the soft error (SET) pulse width should be? I know that is different in different case. Therefore, I am going to set up a random generator to generator the SET pulse width. But what range...
Sorry for the typing error again :(.
When I do the simulation, the code doesn't work what I prefer. I think I need to use two for loop together to change the MAX and MIN value. I am trying to fix it now.
Thanks :)
Thank for your reply
Sorry for my poor english, I didnt get what you mean by wait #1ns? I would like to create a for loop and get the random delay timing between 0 ns to 300ns. It will generate a random delay time each 30ns. (i=0;i<300;i=i+30).
For example
0 ns to 30ns:
j = 20ns -> inject value...
Homework Statement
Hi, I would like to generate a random delay time and value in testbench. This is what I did:
for(i=0;i<300;i=i+30)
begin
j = i + {$random} % (300 - i) // MIN + {$random} % (MAX - MIN )
#j b = {$random} %3;
#3ns b = 3'b000;
end
I want to generate random...
Homework Statement
I am trying to understand a simply CPU which written in system verilog. I understand most of them a part from the red colour part.
import cpu_defs::*;
module IR (CPU_bus.IR_port bus);
logic [WORD_W-1:0] instr_reg;
assign bus.sysbus = bus.Addr_bus ...
Homework Statement
Hi, I am trying to complie my counter (writen in system verilog) using synopsys design compiler. It comes out this error:
The expression in the reset condition of the 'if' statement in this 'always' block can only be a simple identifier or its negation. (ELAB-303)
***...
sorry, 1 more question
can i use count to the counting?not i.
like
if count < 12
...
..
i have try that in my code but it doesn't work. is that becuase count is the output so i cannot use it for internal counting?
Hi all,
i am trying to do a counter using system verilog. The counter will count from 0 to 11 then back to 0 and start the counting again.
Input = rdy, if rdy = 0, start counting.
Output = count
I have done the simulation for my code and it is not working as i prefer. It will...